1. Field of the Invention
The present invention generally relates to frequency dividing circuits, and more particularly to a frequency dividing circuit suitably used for, for example, a frequency converting circuit built in integrated circuits devices for communications.
2. Background of the Invention
FIG. 1 is a circuit diagram of a frequency dividing circuit as described above. The frequency dividing circuit shown in FIG. 1 has an SCFL circuit 1. The term "SCFL" is an abbreviation of Source Coupled Field effect transistor Logic. The SCFL circuit 2 includes a differential amplifier circuit 2, a level-shift diode 3, load resistors 4 and 5, MESFETs 6 and 7 of the depletion type serving as driving transistors, and a MESFET 8 of the depletion type functioning as a constant-current source. The term "MESFET" is an abbreviation of MEtal Semiconductor Field Effect Transistor.
Further, the frequency dividing circuit includes source-follower circuits 9-14, MESFETs 15-20 20 of the depletion type functioning as input transistors, level-shift diodes 21-32 and MESFETs 33-38 of the depletion type functioning as constant-current sources. Furthermore, the frequency dividing circuit includes MESFETs 39 and 40 of the enhancement type, and MESFETs 41 and 42 of the enhancement type. The MESFETs 39 and 40 are turned ON and OFF by an input signal IN which is to be frequency-divided. The MESFETs 41 and 42 are turned ON and OFF by an inverted version IN of the input signal IN (the signal IN has a complementary relationship to the signal IN).
The MESFETs 39 and 40 are alternately turned ON in response to the input signal IN, and the MESFETs 41 and 42 are alternately turned ON in response to the inverted input signal IN. Thereby, frequency-divided signals OUT and OUT which are complementary signals are produced so that the signals OUT and OUT have a frequency half the frequency of the signals IN and IN.
However, the frequency dividing circuit shown in FIG. 1 has a disadvantage in that it needs a large number of structural elements, and a large amount of power is consumed because currents always flow in the differential amplifier circuit 2 and the source-follower circuits 9-14. Further, the frequency dividing circuit shown in FIG. 1 has another disadvantage in that the frequency dividing circuit cannot be driven by a relatively low power supply voltage VDD due to the presence of the level-shift diodes 21-32.
With the above in mind, an improved frequency dividing circuit as shown in FIG. 2 has been proposed. The frequency dividing circuit shown in FIG. 2 includes a BFL circuit 44 functioning as an inverter circuit. The term "BFL" is an abbreviation of a Buffered Field effect transistor Logic. The BFL circuit 44 includes an inverter 45, a MESFET 46 of the depletion type functioning as a load element, and a MESFET 47 of the depletion type serving as a driving element.
The frequency dividing circuit shown in FIG. 2 includes source-follower circuits 48-50, MESFETs 51-53 of the depletion type functioning as input transistors, level-shift diodes 54-59, and MESFETs 60-62 of the depletion type functioning as constant-current sources. Further, the frequency dividing circuit shown in FIG. 2 includes MESFETs 63 and 64 of the enhancement type. The MESFET 63 is turned ON and OFF in response to the input signal IN, and the MESFET 64 is turned ON and OFF in response to its inverted version IN. The MESFETs 63 and 64 are alternately turned ON in response to the signals IN and IN, whereby a frequency-divided output signal OUT having a frequency equal to half that of the input signals is produced.
The frequency dividing circuit shown in FIG. 2 can be configured by a smaller number of parts than that for the circuit shown in FIG. 1. However, the frequency dividing circuit shown in FIG. 2 has a disadvantage in that it needs two power supply sources VDD and VSS, and cannot be driven by a single power supply source. The circuit shown in FIG. 2 has another disadvantage in that currents always flow in the inverter 45 and the source-follower circuits 48-50 and the complementary output signals cannot be produced.
Taking into consideration the above, a further improved frequency dividing circuit as shown in FIG. 3 has been proposed. The circuit shown in FIG. 3 includes DCFL circuits 66-68 functioning as inverter circuits. The term "DCFL" is an abbreviation of Direct Coupled Field effect transistor Logic. Further, the circuit shown in FIG. 3 includes MESFETs 69-71 of the depletion type functioning as load elements, and MESFETs 72-74 of the enhancement type functioning as driving elements.
Furthermore, the circuit shown in FIG. 3 includes MESFETs 75 and 76 of the enhancement type. The MESFET 75 is turned ON and OFF in response to the input signal IN, and the MESFET 76 is turned ON and OFF in response to its inverted version IN. The MESFETs 75 and 76 are alternately turned ON in response to the signals IN and IN, so that the frequency-divided output signal OUT having a frequency equal to half that of the signals IN and IN can be produced.
The frequency dividing circuit shown in FIG. 3 has advantages in that it can be driven by a single power supply source and a relatively low power supply voltage and a smaller amount of power can be consumed therein. However, the circuit shown in FIG. 3 has a disadvantage in that the complementary output signals cannot be obtained.